Manufacturers of integrated circuits (ICs) are required to take precautions to avoid ESD. The design of ESD protection devices depends on the application or circuit to be protected. Applications, such as automotive applications which require high operating voltages, require high ESD robustness and latch-up free operation and ESD protection devices which can operate at the high operating voltages required in automotive applications.
Typically, ESD protection devices are formed as part of the ICs to protect input/output pads and power pads of the ICs. FIG. 1 shows an IC 2 including an ESD protection device 4 coupled to input/output pads 6 and to a device or devices 8 of the IC. The ESD protection device 4 is arranged to become active at a triggering voltage Vt1 and to remain active at a holding voltage Vh so as to limit voltage spikes or discharge on the input/output pads. The ESD protection device 4 thus prevents overload of and damage to the device or devices 8 of the IC.
FIG. 2 shows a collector current-collector voltage curve 10 of a typical prior art bipolar ESD protection device having a maximum voltage Vmax, at which oxide breakdown occurs, a breakdown voltage Vb at which first breakdown occurs, a triggering voltage Vt1, and a holding voltage Vh. The ESD protection device provides ESD protection in the window between the maximum voltage Vmax and the supply voltage Vsup. As can be seen from the curve 10, when the voltage reaches the triggering voltage Vt1, the ESD protection device is active and the device snaps back to the holding voltage Vh. Ron is the resistance of the bipolar ESD protection device once the device is active. In order to correctly protect a circuit, Ron is required to be low so that the voltage remains under the maximum voltage Vmax whilst the ESD protection is active.
In some applications, particularly for automotive applications when the ESD protection window between the supply voltage Vsup and the maximum voltage Vmax is required to be narrow (for example, around 10 volts) in order to prevent latch-up during fast electromagnetic or parasitic transients, there is a further requirement to have an ESD protection device that has no or substantially no snap back. In other words, for some applications it is desirable for the triggering voltage Vt1 to be close to the holding voltage Vh in order to increase the robustness and reliability. For example, in Power Over Ethernet (POE) applications, which specifies for ESD protection a maximum rating of 80 volts and the triggering voltage Vt1 and holding voltage Vh higher than 80 volts, a no snap back ESD protection structure with low on resistance Ron is required.
U.S. Pat. No. 6,707,110 discloses an ESD protection device including a bipolar transistor having an emitter region and base region formed in a weakly doped well region which well region extends a distance d from the emitter region towards the collector region. The ESD protection device further comprises a buried region below the base, emitter and collector regions and thus, the ESD protection device is configured so as to comprise a lateral bipolar transistor and a vertical bipolar transistor. In operation, the holding voltage Vh of the ESD protection device is determined by which of these two transistors snaps back first i.e. which of these two transistors becomes active first when the triggering voltage Vt1 is reached. By varying the distance d, it can be determined which of these two transistors snaps back first and thus, by varying the distance d, the holding voltage Vh can be varied. For lower values of distance d, the holding voltage Vh is determined by the lateral transistor and is lower than for higher values of d when the holding voltage is determined by the vertical transistor. This patent further teaches including an additional high doped region in the weakly doped well region between the emitter and collector region which has the same effect as increasing the distance d. The additional high doped region has the same conductivity type as the weakly doped well region. Although such an arrangement allows for Vh to be increased towards Vt1, by increasing distance d, such an arrangement requires a buried layer in order to realise the vertical bipolar transistor which requires additional manufacturing process steps and so increases the cost of such ESD protection devices. Furthermore, the ESD protection device disclosed in this patent does not allow a holding voltage higher than a value set by the vertical transistor. The value cannot be adjusted in a given technology and is generally too low for protecting high voltage I/O pads. In other words, an arrangement having a buried region, which provides a vertical transistor in operation, is not suited to high voltage applications.
European patent application no. EP 1396887 discloses an ESD protection device comprising a bipolar transistor device and at least one floating region between the emitter and collector regions of the bipolar transistor device. The triggering voltage Vt1 of such a device depends on the doping concentration of semiconductor layer in which the emitter, collector and floating regions are formed and the distance between the floating region and the collector region. This patent explains how to adjust the distance to control the triggering voltage Vt1. However, it does not provide any information on methods to control the snap back, the holding voltage and Ron. Thus, the arrangement disclosed in this patent is not suited for applications requiring high voltage and narrow ESD design windows.
An article entitled ‘ESD Robust Transistors with Variable Trigger and Sustaining Voltages’ by S Pendharkar et al describes an ESD protection structure including two npn bipolar transistors in parallel with a common collector. The I-V curves show no snap back behaviour. However, a partial buried layer is used to adjust the holding voltage Vh and thus, such an arrangement requires additional manufacturing process steps and so increases the cost of such ESD protection devices.
Other ESD protection mechanisms based on MOSFET devices, stacked bipolar transistors, Silicon Controlled Rectifiers (SCR), Bipolar Junction Transistors (BJT), zener diodes are well known. However, these known mechanisms provide ESD protection with snap back and thus, cannot be used in applications requiring very narrow ESD protection windows.
For example, US patent application no. 2001/0007521 describes an ESD protection circuit comprising mainly a BJT having first and second holding voltages and a high triggering current. The second holding voltage is low compared to the first holding voltage. The ESD protection circuit described in this patent application achieves the low second holding voltage at high current by including a floating region in the collector of the BJT, having a conductivity type opposite to that of the collector. The distance between the floating region and the region coupled to the I/O node can be varied to adjust the level of the high current. However, such an ESD protection arrangement has strong snap back and this patent application provides no information on methods to control snap back,
Thus, there is a need for an improved ESD protection device.